The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2018

Filed:

Sep. 21, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Harold M. Kutz, Edmonds, WA (US);

Timothy John Williams, Bellevue, WA (US);

Bert S. Sullam, Bellevue, WA (US);

Warren S. Snyder, Snohomish, WA (US);

James H. Shutt, Seattle, WA (US);

Bruce E. Byrkett, Preston, WA (US);

Monte Mar, Issaquah, WA (US);

Eashwar Thiagarajan, Bothell, WA (US);

Nathan Wayne Kohagen, Redmond, WA (US);

David G. Wright, Woodinville, WA (US);

Mark E Hastings, Mukilteo, WA (US);

Dennis R. Seguine, Temecula, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G01R 31/3177 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31721 (2013.01); H03K 19/173 (2013.01);
Abstract

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.


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