The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Apr. 11, 2017
Applicant:
Innovative Micro Technology, Goleta, CA (US);
Inventors:
Christopher S. Gudeman, Lompoc, CA (US);
Jeffery F. Summers, Santa Barbara, CA (US);
Assignee:
Innovative Micro Technology, Goleta, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); B81C 1/00 (2006.01); B81B 3/00 (2006.01); H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00698 (2013.01); B81B 3/0086 (2013.01); H01L 21/76232 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 23/481 (2013.01); B81B 2201/014 (2013.01); B81B 2207/096 (2013.01); B81C 2201/0171 (2013.01);
Abstract
Described herein is a method and structure for fabricating vias in a semiconductor substrate. The semiconductor substrate is first doped to make it mildly conducting, via holes are formed therein, and a conductive material is deposited in the holes. Using the moderate conductivity of the substrate, the conductive material may be plated into the holes.