The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Feb. 20, 2017
Northwestern University, Evanston, IL (US);
Regents of the University of Minnesota, Minneapolis, MN (US);
Mark C. Hersam, Wilmette, IL (US);
Michael L. Geier, Chicago, IL (US);
Pradyumna L. Prabhumirashi, Chicago, IL (US);
Weichao Xu, Minneapolis, MN (US);
Hyungil Kim, Woodbury, MN (US);
NORTHWESTERN UNIVERSITY, Evanston, IL (US);
REGENTS OF THE UNIVERSITY OF MINNESOTA, Minneapolis, MN (US);
Abstract
A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.