The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Aug. 16, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chia-Ta Hsieh, Tainan, TW;

Chi-Wei Ho, Tainan, TW;

Kao-Chao Lin, Fanlu Township, TW;

Josh Lin, Tainan, TW;

Nai-Chao Su, Tainan, TW;

Shih-Jung Tu, Tainan, TW;

Po-Kai Hsu, Tainan, TW;

Shih-Ching Lee, Taichung, TW;

Chen-Ming Huang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); H01L 27/11526 (2017.01); H01L 27/11521 (2017.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 29/0642 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.


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