The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jan. 07, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Dongjin Lee, Seoul, KR;

Sungho Jang, Seoul, KR;

Jiyoung Kim, Yongin-si, KR;

Kang-Uk Kim, Seoul, KR;

Chan Min Lee, Hwaseong-si, KR;

Juyeon Jang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10885 (2013.01); H01L 21/32139 (2013.01); H01L 27/10888 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01);
Abstract

Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.


Find Patent Forward Citations

Loading…