The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Nov. 18, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Chih-Hung Lu, Hsinchu County, TW;
Ching-Chen Hao, Hsinchu County, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76831 (2013.01); H01L 21/0228 (2013.01); H01L 21/02123 (2013.01); H01L 21/31116 (2013.01); H01L 21/76808 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 21/02164 (2013.01); H01L 21/02167 (2013.01); H01L 2221/1031 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A method of forming an integrated circuit that includes providing a substrate, a metal layer over the substrate, and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer and an ultra-thick metal (UTM) layer is in the via.