The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Mar. 26, 2015
Intel Corporation, Santa Clara, CA (US);
Mahesh Wagh, Portland, OR (US);
Zuoguo Wu, San Jose, CA (US);
Venkatraman Iyer, Austin, TX (US);
Gerald S. Pasdast, San Jose, CA (US);
Mark S. Birrittella, Chippewa Falls, WI (US);
Ishwar Agarwal, Hisslboro, OR (US);
Lip Khoon Teh, Penang, MY;
Su Wei Lim, Penang, MY;
Anoop Kumar Upadhyay, Uttar Pradesh, IN;
Intel Corporation, Santa Clara, CA (US);
Abstract
A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.