The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Jun. 09, 2015
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Yoshiyuki Nakamura, Kawasaki, JP;

Tomoaki Tamura, Kawasaki, JP;

Kouichi Kumaki, Kawasaki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 23/00 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2855 (2013.01); G01R 31/2894 (2013.01); H01L 22/14 (2013.01); H01L 22/20 (2013.01); H01L 24/95 (2013.01);
Abstract

A burn-in test process is omitted for some or all lots. In burn-in necessity determination processing, whether each semiconductor chip requires a burn-in test to be performed is determined based on measurement data obtained in a probe test process. In an assembly process, based on the results of determination made in the burn-in necessity determination processing, the assembled packages are sorted into a first lot which includes packages each including a semiconductor chip determined to require a burn-in test to be performed and a second lot which includes packages each including a semiconductor chip determined to require no burn-in test to be performed. In a burn-in test process, only the packages of the first lot are subjected to a burn-in test.


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