The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2018
Filed:
Nov. 18, 2016
Applicant:
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Inventor:
Gregory Bidal, Grenoble, FR;
Assignee:
STMicroelectronics (Crolles 2) SAS, Crolles, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/119 (2006.01); H01L 29/786 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/28026 (2013.01); H01L 21/28158 (2013.01); H01L 21/7624 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0684 (2013.01); H01L 29/42364 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66477 (2013.01); H01L 29/66636 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/78618 (2013.01);
Abstract
A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.