The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Apr. 20, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Wen-Hsin Lin, Jhubei, TW;

Shin-Cheng Lin, Tainan, TW;

Cheng-Tsung Wu, Taipei, TW;

Yu-Hao Ho, Keelung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 31/112 (2006.01); H01L 29/10 (2006.01); H01L 29/808 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/225 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1058 (2013.01); H01L 21/2253 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 29/66901 (2013.01); H01L 29/808 (2013.01);
Abstract

A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.


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