logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9941332 B1

PDFFull Text
Date of Patent:
Apr. 10, 2018

Filed:

Jan. 19, 2017

Semiconductor memory device and structure

Applicant:

Monolithic 3d Inc., San Jose, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Brian Cronquist, San Jose, CA (US);

Israel Beinglass, Sunnyvale, CA (US);

Zeev Wurman, Palo Alto, CA (US);

Assignee:

MONOLITHIC 3D INC., San Jose, CA (US);

Attorney:

Tran & Associates

Primary Examiner:

Evan Pert

Int. Cl.
CPC ...
H01L 27/10 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 29/04 (2006.01); H01L 29/167 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/105 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/223 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); G11C 13/0021 (2013.01); H01L 27/1052 (2013.01); H01L 27/249 (2013.01); H01L 29/04 (2013.01); H01L 29/167 (2013.01); H01L 29/66568 (2013.01); H01L 29/78 (2013.01); H01L 45/146 (2013.01); H01L 45/1616 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02667 (2013.01); H01L 21/2236 (2013.01); H01L 21/31116 (2013.01); H01L 21/324 (2013.01);
Abstract

A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

Find Patent Forward Citations

Quick Actions:

Or-Bach, Zvi. (2018). Semiconductor memory device and structure (U.S. Patent No. 9941332). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9941332

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…