The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Aug. 16, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jaehee Kim, Yongin-si, KR;

Soonmok Ha, Hwaseong-si, KR;

Jonghyuk Kim, Seoul, KR;

Joonsoo Park, Incheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 27/10814 (2013.01); H01L 27/10826 (2013.01); H01L 27/10852 (2013.01); H01L 27/10855 (2013.01); H01L 27/10879 (2013.01); H01L 27/10885 (2013.01); H01L 28/90 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes forming first and second lower structures including selection elements on first and second chip regions of a substrate, respectively, forming first and second mold layers on the first and second lower structures, respectively, forming first and second support layers on the first and second mold layers, respectively, patterning the first support layer and the first mold layer to form first holes exposing the first lower structure, forming first lower electrodes in the first holes, forming a support pattern including at least one opening by selectively patterning the first support layer while leaving the second support layer, and removing the first mold layer through the opening. A top surface of the support pattern is disposed at a substantially same level as a top surface of the second support layer.


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