The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Jan. 27, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yung-Tai Hsu, Hsinchu County, TW;

Tien-Shang Kuo, Taoyuan, TW;

Yen-Chuan Chen, New Taipei, TW;

Chih-Hao Cheng, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01); H01L 21/784 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/784 (2013.01); H01L 23/544 (2013.01); H01L 23/585 (2013.01); H01L 22/32 (2013.01); H01L 2223/5446 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/94 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/14 (2013.01); H01L 2924/3512 (2013.01);
Abstract

An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region.


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