The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9941172 B1

Date of Patent:

Apr. 10, 2018

Filed:

Aug. 13, 2016

Method for fabricating semiconductor device including a via hole in a mask pattern

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jong-Doo Kim, Yongin-si, KR;

Joong-Won Jeon, Seoul, KR;

Young-Deok Kwon, Suwon-si, KR;

Suk-Joo Lee, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Selim Ahmed

Int. Cl.

CPC ...

H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01);

U.S. Cl.

CPC ...

H01L 21/823475 (2013.01); H01L 21/76816 (2013.01); H01L 23/522 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 21/76804 (2013.01);

Abstract

A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer that comprises a first region and a second region, forming an etch stop pattern for exposing the second region in the first region of the interlayer insulating layer and forming a mask pattern that comprises a first via-hole that exposes an upper surface of the etch stop pattern and a second via-hole that penetrates the interlayer insulating layer on the interlayer insulating layer and the etch stop pattern.

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