The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2018
Filed:
Apr. 01, 2015
Qualcomm Incorporated, San Diego, CA (US);
Shiqun Gu, San Diego, CA (US);
Vidhya Ramachandran, Cupertino, CA (US);
Christine Sung-An Hau-Riege, Fremont, CA (US);
John Jianhong Zhu, San Diego, CA (US);
Jeffrey Junhao Xu, San Diego, CA (US);
Jihong Choi, San Diego, CA (US);
Jun Chen, San Diego, CA (US);
Choh Fei Yeap, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.