The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Nov. 16, 2016
Applicant:

The Regents of the University of Michigan, Ann Arbor, MI (US);

Inventors:

Yalcin Yilmaz, Ann Arbor, MI (US);

Pinaki Mazumder, Ann Arbor, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/56 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/77 (2013.01);
Abstract

A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node, and an interpretation circuit electrically connected to the node and configured to interpret a voltage at the node and to indicate a resistive state of the memory element based on the voltage at the node. The interpretation circuit includes one or more active devices, one or more passive devices each electrically connected to a respective one of the active devices, and one or more comparators each electrically connected to a respective one of the active devices. Each of the active devices and the passive device electrically connected thereto are configured to provide a voltage level to the respective comparator to which the active device is connected. The comparator(s) are configured to indicate the resistive state of the memory element based on the provided voltage level(s).


Find Patent Forward Citations

Yilmaz, Yalcin. (2018). Multi-level resistive memory structure (U.S. Patent No. 9941003). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9941003

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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