The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Jan. 31, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Trevis Chandler, Dundas, CA;

Jung Ko, Santa Clara, CA (US);

Kenneth Duong, San Jose, CA (US);

Dipak Sikdar, Milpitas, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/418 (2013.01);
Abstract

A programmable integrated circuit may include configuration random-access memory (CRAM) cells and lookup table random-access memory (LUTRAM) cells. The programmable integrated circuit may include a CRAM column and at least two LUTRAM columns, a first portion of which is operable as LUTRAM cells and a second portion of which is reused as CRAM cells. Each of the memory cells have a configuration write port and a read port. The configuration write ports of the first portion may be gated, whereas the configuration write ports of the second portion lack gating logic. The read port of the memory cells in the LUTRAM columns may be masked only when the first portion of cells are operated in RAM mode and are currently being accessed.


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