The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Dec. 30, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Kyung-Whan Kim, Gyeonggi-do, KR;

Dong-Uk Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 13/40 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1006 (2013.01); G06F 13/161 (2013.01); G06F 13/4027 (2013.01); G06F 13/4286 (2013.01); G11C 7/22 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01); G11C 7/1018 (2013.01); G11C 7/1042 (2013.01); G11C 7/1045 (2013.01); G11C 7/1072 (2013.01); G11C 2207/005 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2281 (2013.01);
Abstract

A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.


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