The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2018
Filed:
Nov. 23, 2015
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Loren Blair Reiss, Raleigh, NC (US);
Fred Staples Stivers, Raleigh, NC (US);
Scott Gerald Bare, Creedmoor, NC (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); H04L 7/04 (2006.01); G06F 13/20 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/20 (2013.01); H04L 7/033 (2013.01); H04L 7/04 (2013.01);
Abstract
The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include operatively connecting one or more lane modules of an integrated circuit (IC) to form one or more links. The method may further include associating a FIFO reset generator with each of the one or more lane modules and receiving a signal from the FIFO reset generator at a synchronization FIFO. The method may also include aligning, at the synchronization FIFO, one or more enqueue pointers and dequeue pointers.