The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2018
Filed:
Jan. 06, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Anne Hughes, Austin, TX (US);
Bikram Banerjee, Bengaluru, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A memory controller system optimally controls access to a memory device having a plurality of integrated circuit (IC) chips disposed in a non-uniform stack configuration within a three-dimensional stacked (3DS) structure. A memory profiling portion executes to determine the non-uniform stack configuration. A virtual rank mapping portion configured to assign virtual ranks to chip locations actually defined by the non-uniform stack configuration. An address conversion portion executes to convert an unoptimized address definable with reference to a uniform stack configuration to an optimized address defined with reference to the non-uniform stack configuration. The addressing overhead during monitoring of data access operations to the memory device is optimized.