The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Mar. 31, 2016
Applicant:

Optimum Semiconductor Technologies, Inc., Tarrytown, NY (US);

Inventors:

Mayan Moudgill, Chappaqua, NY (US);

Gary Nacer, Morris Plains, NJ (US);

C. John Glossner, Nashua, NH (US);

A. Joseph Hoane, Yonkers, NY (US);

Paul Hurtley, White Plains, NY (US);

Murugappan Senthilvelan, Carmel, NY (US);

Pablo Balzola, Madrid, ES;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 9/30 (2018.01); G06F 3/06 (2006.01); G06F 12/0875 (2016.01); G06F 12/0893 (2016.01); G06F 12/1009 (2016.01); G06F 12/0862 (2016.01); G06F 9/32 (2018.01); G06F 9/355 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30029 (2013.01); G06F 3/0604 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G06F 9/30 (2013.01); G06F 9/3013 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30054 (2013.01); G06F 9/30058 (2013.01); G06F 9/322 (2013.01); G06F 9/355 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 12/1009 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01);
Abstract

A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.


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