The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2018
Filed:
Jul. 08, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Taranjit Singh Kukal, Nirankari Colony, IN;
Balvinder Singh, Faridabad, IN;
Steven R. Durrill, Campbell, CA (US);
Arnold Ginetti, Antibes, FR;
Vikrant Khanna, Noida, IN;
Abhishek Dabral, Noida, IN;
Madhur Sharma, Ghaziabad, IN;
Nikhil Gupta, Vasant Kunj, IN;
Ritabrata Bhattacharya, Malviya Nagar, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.