Clock gating verification during rtl stage of integrated circuit design

Abstract

Embodiments provided herein include a method for a clock gating verification during a register transfer level (RTL) circuit design stage, including: obtaining clock gating information defined in a clock gating (CG) specification according to a clock gating format, wherein the clock gating information describes a target clock gating behavior of at least a first gated clock signal utilized by an integrated circuit design, the CG specification comprises a template structure defining a relationship between an output gated clock and an input clock, based on an enable condition, and a top mapping associating top level signals, including the first gated clock signal, of the integrated circuit design to the template structure; and automatically generating a first clock gating (CG) checker to verify a clock gating behavior, based on an expected output time and an expected gated time during testing of the integrated circuit design.