The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2018
Filed:
Feb. 14, 2016
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventor:
Yao-Chun Su, Hsinchu, TW;
Assignee:
MEDIATEK INC., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); G06F 13/368 (2006.01); G06F 13/40 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06F 13/368 (2013.01); G06F 13/4068 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 25/065 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06527 (2013.01);
Abstract
A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.