The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Sep. 26, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Simon C. Steely, Jr., Hudson, NH (US);

Samantika S. Sury, Westford, MA (US);

William C. Hasenplaugh, Boston, MA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0817 (2016.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0824 (2013.01); G06F 12/0811 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/2542 (2013.01);
Abstract

Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core to send a request for the cache line from the first core, moving logic to cause a move of the cache line between the first core and a memory and to update a tag directory of the move, and cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second core. A method to control cache line coherency may include creating a chain home in a tag directory from a request for a cache line in a first processor core from a second processor core to cause the cache line to be sent from the tag directory to the second processor core.


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