The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Nov. 29, 2016
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Tohru Kawai, Ibaraki, JP;

Yasutaka Nakashiba, Ibaraki, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/122 (2006.01); H01L 21/265 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/36 (2006.01); G02B 6/12 (2006.01);
U.S. Cl.
CPC ...
G02B 6/122 (2013.01); G02B 6/12004 (2013.01); H01L 21/26506 (2013.01); H01L 21/76898 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 29/36 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12123 (2013.01); G02B 2006/12142 (2013.01); G02B 2006/12176 (2013.01);
Abstract

Provided is an SOI substrate which has a substrate, an insulating layer formed over the substrate, and a semiconductor layer formed over the insulating layer. Optical waveguides are formed in the semiconductor layer of the SOI substrate. This substrate has a low resistance semiconductor layer and a high resistance semiconductor layer thereover. Further, wirings which are formed through insulating films are provided on the optical waveguides. In this manner, the low resistance semiconductor layer is arranged in the surface part of the substrate of the insulating films, thereby restraining an eddy current generated in the substrate due to an electric signal transmitted through the wirings.


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