The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Mar. 08, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Ji Quan Liu, Shanghai, CN;

Chun Lei Gong, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01); H01L 31/0392 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/762 (2013.01); H01L 21/7624 (2013.01); H01L 21/76248 (2013.01); H01L 21/845 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78603 (2013.01);
Abstract

A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.


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