The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Feb. 25, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventor:

David Paul Brunco, Latham, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01); H01L 29/167 (2006.01); H01L 29/10 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01);
Abstract

At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.


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