The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2018
Filed:
May. 02, 2016
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Zhonghai Shi, Austin, TX (US);
Marc L. Tarabbia, Austin, TX (US);
CIRRUS LOGIC, INC., Austin, TX (US);
Abstract
A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the integrated circuit. These thin vertical structures can be configured to operate as an insulator in a capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.