The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Sep. 08, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Emre Alptekin, Fishkill, NY (US);

Ravikumar Ramachandran, Pleasantville, NY (US);

Viraj Y. Sardesai, Malta, NY (US);

Reinaldo A. Vega, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 21/321 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/283 (2013.01); H01L 21/28008 (2013.01); H01L 21/3212 (2013.01); H01L 29/41775 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01); H01L 21/76829 (2013.01);
Abstract

A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.


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