The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Dec. 26, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chih-Ming Chen, Hsinchu, TW;

Tsu-Hui Su, Taipei, TW;

Szu-Yu Wang, Hsinchu, TW;

Chung-Yi Yu, Hsin-Chu, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02247 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 29/42344 (2013.01); H01L 29/42348 (2013.01); H01L 29/66833 (2013.01); H01L 29/7923 (2013.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01);
Abstract

The present disclosure relates to a structure and method for reducing dangling bonds around quantum dots in a memory cell. In some embodiments, the structure has a semiconductor substrate having a tunnel dielectric layer disposed over it and a plurality of quantum dots disposed over the tunnel dielectric layer. A passivation layer is formed conformally over outer surfaces of the quantum dots and a top dielectric layer is disposed conformally around the passivation layer. The passivation layer can be formed prior to forming the top dielectric layer over the quantum dots or after forming the top dielectric layer. The passivation layer reduces the dangling bonds at an interface between the quantum dots and the top dielectric layer, thereby preventing trap sites that may hinder operations of the memory cell.


Find Patent Forward Citations

Loading…