The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2018
Filed:
Feb. 02, 2016
Freescale Semiconductor, Inc., Austin, TX (US);
Perry H. Pelley, Austin, TX (US);
Anirban Roy, Austin, TX (US);
NXP USA, Inc., Austin, TX (US);
Abstract
A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.