The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Apr. 01, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rotem Banin, Pardes-Hana, IL;

Assaf Ben-Bassat, Haifa, IL;

Evgeny Shumaker, Nesher, IL;

Ofir Degani, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/50 (2006.01); G04F 10/00 (2006.01); H03M 1/04 (2006.01); H03K 3/037 (2006.01); H03K 19/23 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01); H03K 3/037 (2013.01); H03K 19/23 (2013.01); H03M 1/04 (2013.01);
Abstract

A method and apparatus for determining a difference between signal edges in two signals includes a multiple stage converter where each stage determines which of the two signals has an earlier signal edge, outputs a value corresponding to that determination, and then applies a delay to the earlier signal that is equal to half of the delay applied by the next previous stage. The stages examine smaller and smaller intervals to the sought-after signal edge. Each stage includes a plurality of logic elements. If all logic elements in the stage output the same signal, the edge position is clear. If some of the logic elements in the stage vote differently than others in the state due to differences in setup time for the different elements, the edge location has been found within the sensing band of the stage.


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