The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Jul. 18, 2016
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Anirban Roy, Austin, TX (US);
Michael A. Sadd, Austin, TX (US);
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/289 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01); G11C 13/00 (2006.01); G11C 13/02 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0069 (2013.01); G11C 13/025 (2013.01);
Abstract
A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and a second pair of memory cells coupled to the slave latch circuit in parallel with the first pair of memory cells. The first and second pair of memory cells are configured to store data from the slave latch circuit, and to restore data to the slave latch circuit.