The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Jan. 30, 2017
Applicant:

J-devices Corporation, Usuki-shi, Oita, JP;

Inventors:

Hiroaki Matsubara, Yokohama, JP;

Tomoshige Chikai, Yokohama, JP;

Naoki Hayashi, Yokohama, JP;

Toshihiro Iwasaki, Yokohama, JP;

Assignee:

J-DEVICES CORPORATION, Usuki-shi, Oita, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/538 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5386 (2013.01);
Abstract

An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.


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