Reducing select gate injection disturb at the beginning of an erase operation

Abstract

A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.