The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Mar. 25, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shigeki Tomishima, Portland, OR (US);

Shih-Lien L. Lu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 5/02 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 7/20 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 11/4072 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 5/025 (2013.01); G11C 7/08 (2013.01); G11C 7/1006 (2013.01); G11C 7/1045 (2013.01); G11C 7/20 (2013.01); G11C 7/22 (2013.01); G11C 11/4072 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 2207/005 (2013.01); G11C 2207/105 (2013.01); G11C 2207/107 (2013.01);
Abstract

An apparatus comprises: a source array of memory cells with associated source sense amplifiers; a destination array of memory cells with associated destination sense amplifiers; and logic to activate a source word-line (WL) to select a row of memory cells within the source array such that data in the selected row of memory cells is latched by the associated source sense amplifiers, wherein the logic to activate a destination WL to select a row of memory cells within the destination array such that data in the selected row of memory cells is latched by the associated destination sense amplifiers, and wherein the source and destination arrays of memory cells are within a same bank of a memory.


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