The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Apr. 01, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert A. Branch, Portland, OR (US);

Murugasamy K. Nachimuthu, Beaverton, OR (US);

Sundar Muthusamy, Lexington, SC (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01); G06F 9/44 (2018.01); G11C 14/00 (2006.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 9/4401 (2013.01); G06F 12/10 (2013.01); G11C 14/009 (2013.01); G11C 14/0063 (2013.01); G11C 14/0081 (2013.01); G06F 2212/1044 (2013.01);
Abstract

Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.


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