Multi-bank non-volatile memory apparatus with high-speed bus

Abstract

Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.