The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Mar. 29, 2016
Applicant:
Tokyo Ohka Kogyo Co., Ltd., Kawasaki-shi, JP;
Inventors:
Tomoya Kumagai, Kawasaki, JP;
Takahiro Eto, Kawasaki, JP;
Assignee:
TOKYO OHKA KOGYO CO., LTD., Kawasaki-Shi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); C11D 7/50 (2006.01); G03F 7/42 (2006.01); B08B 3/08 (2006.01); C11D 7/08 (2006.01); C11D 7/26 (2006.01); C11D 7/32 (2006.01);
U.S. Cl.
CPC ...
C11D 7/5022 (2013.01); B08B 3/08 (2013.01); C11D 7/08 (2013.01); C11D 7/263 (2013.01); C11D 7/3209 (2013.01); C11D 7/5009 (2013.01); G03F 7/423 (2013.01); G03F 7/425 (2013.01); H01L 21/0206 (2013.01); H01L 21/02063 (2013.01); H01L 21/02068 (2013.01);
Abstract
A cleaning liquid for lithography, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for includes an alkali or an acid, a solvent, and a silicon compound generating a silanol group through hydrolysis. The method forms a metal wiring layer by embedding a metal in an etching space formed in a low dielectric constant layer of a semiconductor multilayer laminate. In this method, the semiconductor multilayer laminate is cleaned using the cleaning liquid for lithography, after formation of the etching space.