The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

May. 24, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventor:

Roy McLaren, Gilbert, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/19 (2006.01); H03F 3/195 (2006.01); H03F 1/56 (2006.01); H03F 3/60 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0288 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H03F 3/602 (2013.01); H03F 2200/387 (2013.01); H03F 2200/405 (2013.01); H03F 2200/408 (2013.01); H03F 2200/451 (2013.01); H03F 2200/541 (2013.01);
Abstract

A Doherty amplifier includes an output combining network that has a first combining network input coupled to a main amplifier path, a lowest-order combining network input coupled to a lowest-order peaking amplifier path, and N−2 additional combining network inputs coupled to other peaking amplifier paths. A final summing node is coupled to the combining network output, and is directly coupled to the first combining network input. N−2 intermediate summing nodes are coupled to the N−2 additional combining network inputs. An offset line is coupled between the lowest-order combining network input and a lowest-order summing node. A longest phase delay imparted by the output combining network on a peaking RF signal between the lowest-order combining network input and the final summing node is greater than all other phase delays imparted on any other RF signal provided to the first combining network input and the N−2 additional combining network inputs.


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