The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jul. 04, 2016
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Chien-Te Wu, Tainan, TW;

Chien-Tsai Li, Hsinchu, TW;

Cheng-Chung Lo, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H01L 23/498 (2006.01); H01L 21/683 (2006.01); H05K 1/03 (2006.01); H05K 3/00 (2006.01); H05K 1/11 (2006.01); H05K 3/12 (2006.01); H05K 3/40 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/6833 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H05K 1/0306 (2013.01); H05K 1/115 (2013.01); H05K 3/002 (2013.01); H05K 3/0023 (2013.01); H05K 3/0029 (2013.01); H05K 3/1275 (2013.01); H05K 3/4007 (2013.01); H05K 3/4038 (2013.01); Y10T 29/49165 (2015.01);
Abstract

Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed.


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