The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2018
Filed:
Jul. 26, 2011
Rajesh M. Sankaran, Portland, OR (US);
Altug Koker, El Dorado Hills, CA (US);
Philip R. Lantz, Cornelius, OR (US);
Asit K. Mallick, Saratoga, CA (US);
James B. Crossland, Banks, OR (US);
Aditya Navale, Folsom, CA (US);
Gilbert Neiger, Portland, OR (US);
Andrew V. Anderson, Forest Grove, OR (US);
Rajesh M. Sankaran, Portland, OR (US);
Altug Koker, El Dorado Hills, CA (US);
Philip R. Lantz, Cornelius, OR (US);
Asit K. Mallick, Saratoga, CA (US);
James B. Crossland, Banks, OR (US);
Aditya Navale, Folsom, CA (US);
Gilbert Neiger, Portland, OR (US);
Andrew V. Anderson, Forest Grove, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.