The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jul. 29, 2015
Applicant:

Freescale Semiconductor Inc., Austin, TX (US);

Inventors:

Roman Nos, Petach Tikva, IL;

Noam Efrati, Beer Sheva, IL;

Sagi Gurfinkel, Kfar Warburg, IL;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/863 (2013.01); H04L 12/721 (2013.01); H04L 29/12 (2006.01);
U.S. Cl.
CPC ...
H04L 47/6215 (2013.01); H04L 45/38 (2013.01); H04L 45/66 (2013.01); H04L 61/6022 (2013.01);
Abstract

In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.


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