The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jul. 12, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

David Paul Brunco, Latham, NY (US);

Jeffrey Bowman Johnson, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/225 (2006.01); H01L 21/02 (2006.01); H01L 29/167 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02529 (2013.01); H01L 21/2251 (2013.01); H01L 21/26513 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 29/1033 (2013.01); H01L 29/1083 (2013.01); H01L 29/167 (2013.01);
Abstract

Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.


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