The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jan. 14, 2013
Applicant:

Soitec, Crolles, FR;

Inventors:

Francois Boedt, Meylan, FR;

Roland Brun, Varces, FR;

Olivier Ledoux, Grenoble, FR;

Eric Butaud, Grenoble, FR;

Assignee:

Soitec, Bernin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/66 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76254 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 29/36 (2013.01);
Abstract

The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.


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