The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Aug. 20, 2015
Applicant:

Oracle International Corporation, Redwood Shores, CA (US);

Inventors:

Kiran Vedantam, Santa Clara, CA (US);

James G. Ballard, Palo Alto, CA (US);

Hsiangwen Lin, Menlo Park, CA (US);

Assignee:

ORACLE INTERNATIONAL CORPORATION, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); H01L 27/0207 (2013.01);
Abstract

Systems, methods, and other embodiments associated with mitigating wire capacitance are described. In one embodiment, a method includes loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit. The design defines layers of the integrated circuit and connections between structures and wire interconnects in the layers. The example method may also include generating, by at least the processor, a structured topology in the design by successively routing the wire interconnects throughout the layers according to coordinates of the structures in the design and weighted values associated with each of the structures to mitigate wire capacitance of the wire interconnects.


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