The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Dec. 07, 2016
Applicants:

University of Electronic Science and Technology of China, Chengdu, CN;

Institute of Electronic and Information Engineering IN Dongguan, Uestc, Dongguan, CN;

Inventors:

Jinping Zhang, Chengdu, CN;

Zehong Li, Chengdu, CN;

Jingxiu Liu, Chengdu, CN;

Min Ren, Chengdu, CN;

Bo Zhang, Chengdu, CN;

Zhaoji Li, Chengdu, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/74 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/747 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7424 (2013.01); H01L 21/02233 (2013.01); H01L 21/26586 (2013.01); H01L 21/3065 (2013.01); H01L 29/1095 (2013.01); H01L 29/408 (2013.01); H01L 29/66386 (2013.01); H01L 29/747 (2013.01); H01L 29/78 (2013.01);
Abstract

A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.


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