The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Oct. 20, 2015
Applicant:

Intel Corporation;

Inventors:

John B. Halbert, Beaverton, OR (US);

Kuljit S. Bains, Olympia, WA (US);

Debaleena Das, Los Gatos, CA (US);

Bill Nale, Livermore, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 13/00 (2006.01); G06F 11/08 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1004 (2013.01); G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/08 (2013.01); G06F 13/00 (2013.01);
Abstract

Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.


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