The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2018

Filed:

Oct. 28, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Theodros Yigzaw, Sherwood, OR (US);

Mohan J. Kumar, Aloha, OR (US);

Hisham Shafi, Akko, IL;

Ron Gabor, Hertzliya, IL;

Ashok Raj, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/07 (2006.01); G06F 9/30 (2018.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 9/3004 (2013.01); G06F 9/3016 (2013.01); G06F 9/30101 (2013.01); G06F 11/0721 (2013.01); G06F 11/0784 (2013.01); G06F 11/0787 (2013.01); G06F 11/0793 (2013.01); G06F 12/00 (2013.01);
Abstract

In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.


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